VR2R-0079

① SA Source

Context Before

The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while

Evidence

the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.

Context After

Transistor count has climbed 60% to 336 billion.

② Atomic Claim

較大的 NVLink 6 chiplet 位於晶片另一端,配置 36 條 custom 400G SerDes links,使連到全部 72 顆 Rubin GPU 的 NVLink bandwidth 提升至 2 倍。

  • Epistemic Mode: ASSERTED
  • Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/NVLink",
        "label": "NVLink 6"
      },
      "role": "interconnect"
    },
    {
      "node": {
        "id": "04_knowledge_base/Chiplet architecture",
        "label": "chiplet"
      },
      "role": "architecture"
    },
    {
      "node": {
        "id": "04_knowledge_base/SerDes",
        "label": "SerDes"
      },
      "role": "serdes"
    },
    {
      "node": {
        "id": "04_knowledge_base/Vera Rubin",
        "label": "Rubin"
      },
      "role": "platform"
    },
    {
      "node": {
        "id": "04_knowledge_base/GPU",
        "label": "GPU"
      },
      "role": "compute_device"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "36",
      "400G",
      "2x",
      "72"
    ],
    "temporal_mentions": []
  },
  "relation_type": "NVLINK6_CHIPLET_SCALEUP_CONFIGURATION"
}

④ Canonical Entity Mapping

RoleSurface LabelCanonical Target
interconnectNVLink 6NVLink
architecturechiplet04_knowledge_base/Chiplet architecture
serdesSerDesSerDes
platformRubin04_knowledge_base/Vera Rubin
compute_deviceGPUGPU

⑤ Human Review

請在 Properties 逐項確認:

  • 原文 → Atomic Claim 是否忠實
  • Atomic Claim → Semantic Frame 是否忠實
  • Canonical Entity mapping 是否正確
  • Epistemic mode 是否保留原文語氣
  • 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。