VR2R-0077_r1

VR2R-0077

① SA Source

• Source: 開啟完整 SA 文章
• Section: Rubin
• Line hint: 65

Context Before

While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. Micron is well behind Samsung and

Evidence

Hynix and we believe they are effectively out of the picture for Rubin HBM4.

Context After

The NVLink-C2C chiplet houses the SerDes for the Vera CPU connection, doubled in bandwidth to 1.8TB/s, while the larger NVLink 6 chiplet on the other end of the chip features 36 custom ‘400G’ SerDes links for 2x NVLink bandwidth to all 72 Rubin GPUs.

② Atomic Claim

……Hynix；SemiAnalysis 並認為 they 在 Rubin HBM4 的競爭中實際已經出局。

• Epistemic Mode: EXPECTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "CLAIM_ONLY",
  "qualifiers": {
    "condition_text": "承接 VR2R-0076；they 的指涉不可由此 atomic claim 單獨安全解析",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "reason": "EXTRACTION_FRAGMENT_WITH_AMBIGUOUS_PRONOUN",
  "statement": "……Hynix；SemiAnalysis 並認為 they 在 Rubin HBM4 的競爭中實際已經出局。"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
—	—	—

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。