VR2R-0073_r1

VR2R-0073

① SA Source

• Source: 開啟完整 SA 文章
• Section: Rubin
• Line hint: 65

Context Before

On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025. In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.

Evidence

While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements

Context After

and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4.

② Atomic Claim

Nvidia 的目標是 22TB/s，但 SemiAnalysis 了解 memory suppliers 在達成 Nvidia 要求上仍面臨挑戰。

• Epistemic Mode: ATTRIBUTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "attribute": "TARGET_MEMORY_BANDWIDTH",
  "context_nodes": [],
  "entity": {
    "id": "02_companies/NVDA",
    "label": "Nvidia"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": "memory suppliers 為 generic category，未 canonicalized",
    "numeric_mentions": [
      "22TB/s"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "22TB/s"
    ],
    "value_text": "目標為 22TB/s；memory suppliers 達標仍有挑戰。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	Nvidia	NVDA

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。