VR2R-0072_r1

VR2R-0072

① SA Source

• Source: 開啟完整 SA 文章
• Section: Rubin
• Line hint: 63

Context Before

On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300. Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025.

Evidence

In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.

Context After

While Nvidia is targeting 22TB/s, we understand that memory suppliers are having challenges hitting Nvidia’s requirements and we see it likely that initial shipments will come in slightly below at closer to 20TB/s. We have discussed the implications to SK Hynix, Samsung, and Micron extensively for Accelerator and HBM model subscribers. Micron is well behind Samsung and Hynix and we believe they are effectively out of the picture for Rubin HBM4.

② Atomic Claim

為追上 AMD MI450 的 memory bandwidth，Nvidia 要求 DRAM suppliers 提供更高的 HBM4 pin speed，且明顯高於 JEDEC 的 HBM4 規範。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "02_companies/NVDA",
        "label": "Nvidia"
      },
      "role": "requester"
    },
    {
      "node": {
        "id": "02_companies/AMD",
        "label": "AMD"
      },
      "role": "competitive_reference"
    },
    {
      "node": {
        "id": "04_knowledge_base/AMD MI450X",
        "label": "MI450"
      },
      "role": "competitive_product"
    },
    {
      "node": {
        "id": "04_knowledge_base/HBM4",
        "label": "HBM4"
      },
      "role": "memory"
    },
    {
      "node": {
        "id": "04_knowledge_base/DRAM",
        "label": "DRAM"
      },
      "role": "supplier_category"
    },
    {
      "node": {
        "id": "04_knowledge_base/JEDEC",
        "label": "JEDEC"
      },
      "role": "standard"
    }
  ],
  "qualifiers": {
    "condition_text": "requested pin speeds are well above JEDEC HBM4 specification",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "REQUESTS_ABOVE_SPEC_HBM4_PIN_SPEED"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
requester	Nvidia	NVDA
competitive_reference	AMD	AMD
competitive_product	MI450	04_knowledge_base/AMD MI450X
memory	HBM4	HBM4
supplier_category	DRAM	DRAM
standard	JEDEC	JEDEC

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。