VR2R-0071_r1

VR2R-0071

① SA Source

• Source: 開啟完整 SA 文章
• Section: Rubin
• Line hint: 63

Context Before

On the memory front, the move to HBM4 means double the bus width per stack, running at 10.8 GT/s for 22TB/s total bandwidth or 2.75x Blackwell at the same 288GB capacity as GB300.

Evidence

Memory bandwidth has been upgraded significantly from the original 13TB/s advertised at GTC 2025.

Context After

In order to catch up to AMD MI450’s memory bandwidth, Nvidia requested much higher HBM4 pin speeds from the DRAM suppliers - well above the speeds that was in the JEDEC specification for HBM4.

② Atomic Claim

Memory bandwidth 相較 GTC 2025 當時公布的原始 13TB/s 規格已大幅提升。

• Epistemic Mode: ASSERTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "frame_type": "CLAIM_ONLY",
  "qualifiers": {
    "condition_text": "本 atomic claim 未明示具體 memory product",
    "numeric_mentions": [
      "13TB/s",
      "2025"
    ],
    "temporal_mentions": [
      "GTC 2025"
    ]
  },
  "reason": "MEMORY_SUBJECT_IMPLICIT_IN_EXTRACTION",
  "statement": "Memory bandwidth 相較 GTC 2025 當時公布的原始 13TB/s 規格已大幅提升。"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
—	—	—

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。