clm_874c977bf267426c82e4d8933c9a86d3_r1

IX2-0585

① SA Source

• Source: 開啟完整 SA 文章
• Section: Migration to Multi Turn Real Multi-Turn Chat and Agentic Coding Datasets
• Line hint: 808

Context Before

Migration to Multi Turn Real Multi-Turn Chat and Agentic Coding Datasets

Currently, InferenceX uses completely random tokens as input for benchmarking. We then vary the ISL/OSL uniformly subject to the distribution [ISL*0.8, ISL], similarly for OSL. Because of the random data, we disable prefix caching in all our benchmarks, as the expected value of a prefix cache hit rate on completely random data is 0%. Furthermore, all the random data is single-turn, meaning each conversation contains only one prompt and one response. While this provides a good baseline Pareto frontier, it is not a practical benchmark setup that mimics real-world production inference workloads.

Evidence

On the other hand, in scenarios where the GPU KV cache is stressed and blocks are offloaded to the CPU, we expect the GBs to excel as these chips have 900GB/s bidirectional CPU-GPU bandwidth

Context After

The point is: real-world multiturn datasets test more SOTA inference engine features and can capture more nuanced and robust performance data across all chips.

With the rise of Claude Code, Codex, and Kimi, it is becoming increasingly important to benchmark performance in agentic coding scenarios. Like above, these scenarios are multi-turn but also include extremely long context conversations as well as tool use. In the next few months, we plan on creating a benchmark suite that will most accurately capture the performance of open models in these agentic coding scenarios across all chips.

② Atomic Claim

另一方面，當 GPU KV cache 壓力提高、blocks 被 offload 到 CPU 時，SemiAnalysis 預期 GB 系列晶片會具優勢，因其具備 900GB/s 雙向 CPU-GPU bandwidth。

• Epistemic Mode: EXPECTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "attribute": "BANDWIDTH",
  "context_nodes": [
    {
      "id": "04_knowledge_base/KV cache",
      "label": "KV cache"
    },
    {
      "id": "04_knowledge_base/CPU",
      "label": "CPU"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/GPU",
    "label": "GPU"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "900GB/s"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "900GB/s"
    ],
    "value_text": "另一方面，當 GPU KV cache 壓力提高、blocks 被 offload 到 CPU 時，SemiAnalysis 預期 GB 系列晶片會具優勢，因其具備 900GB/s 雙向 CPU-GPU bandwidth。"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	GPU	GPU
context_0	KV cache	04_knowledge_base/KV cache
context_1	CPU	CPU

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。