clm_efcb5f30c44d487badf3a9ec59430a2f_r1

2025-11-28_tpuv7-google-takes-a-swing-at-the::TPU7-0014

① SA Source

• Source: 開啟完整 SA 文章
• Section: Ironwood Rack Architecture
• Line hint: 357

Context Before

Source: SemiAnalysis, Google

An innovative design of TPU’s liquid cooling is that the flow rate of the coolant is actively controlled by the valves. This enables much more efficient cooling as the flow can be adjusted depending on the amount of workload that each chip has at any given time. Google’s TPU has also long adopted vertical power delivery, in which the VRM modules of the TPUs are on the other side of the PCB board. These VRM modules also require a cold plate for cooling.

Evidence

The scale up connections between the TPU trays are all over external copper cables or optics, which will be explained in the ICI section below. The connection between the TPU tray and the CPU tray is also over PCIe DAC cable.

Context After

Inter-Chip Interconnect (ICI) – The Key to Expanding Scale-Up World Size

The building block of Google’s ICI scale-up network for TPUv7 is a 4x4x4 3D torus consisting of 64 TPUs. Each 4x4x4 cube of 64 TPUs maps to one physical rack of 64 TPUs. This is an ideal dimension as all 64 TPUs can be connected electrically to each other and still fit in a physical rack.

② Atomic Claim

TPU tray 間 scale-up 以 external copper/optics；TPU tray 與 CPU tray 之間以 PCIe DAC cable 連接。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/TPU",
        "label": "TPU"
      },
      "role": "accelerator"
    },
    {
      "node": {
        "id": "04_knowledge_base/Copper",
        "label": "Copper"
      },
      "role": "medium"
    },
    {
      "node": {
        "id": "04_knowledge_base/CPU",
        "label": "CPU"
      },
      "role": "cpu"
    },
    {
      "node": {
        "id": "04_knowledge_base/PCIe",
        "label": "PCIe"
      },
      "role": "protocol"
    }
  ],
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "TPU_RACK_INTERCONNECT_MEDIA"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
accelerator	TPU	TPU
medium	Copper	Copper
cpu	CPU	CPU
protocol	PCIe	PCIe

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。