2025-11-28_tpuv7-google-takes-a-swing-at-the::TPU7-0015
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Inter-Chip Interconnect (ICI) – The Key to Expanding Scale-Up World Size - Line hint:
361
Context Before
Overall, the TPU rack design is much simpler than that of the Nvidia Oberon NVL72 design, which has a much higher density and utilizes a backplane to connect GPUs to scale up switches. The scale up connections between the TPU trays are all over external copper cables or optics, which will be explained in the ICI section below. The connection between the TPU tray and the CPU tray is also over PCIe DAC cable.
Inter-Chip Interconnect (ICI) – The Key to Expanding Scale-Up World Size
Evidence
Context After

Source: Google, SemiAnalysis
② Atomic Claim
TPUv7 ICI 基本單元是 4×4×4 3D Torus、共 64 TPU,且一個 64-TPU cube 對應一個 physical rack。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "ici_rack_building_block",
"context_nodes": [
{
"id": "04_knowledge_base/3D Torus",
"label": "3D Torus"
},
{
"id": "04_knowledge_base/Scale-up network",
"label": "Scale-up network"
}
],
"entity": {
"id": "04_knowledge_base/TPUv7",
"label": "TPUv7"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"4x4x4",
"64"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"4x4x4",
"64"
],
"value_text": "4x4x4 3D torus = 64 TPUs = one physical rack"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | TPUv7 | TPUv7 |
| context_0 | 3D Torus | 04_knowledge_base/3D Torus |
| context_1 | Scale-up network | 04_knowledge_base/Scale-up network |
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。