clm_a5acd300926e444594bcd497d695eea6_r1

2025-11-28_tpuv7-google-takes-a-swing-at-the::TPU7-0021

① SA Source

• Source: 開啟完整 SA 文章
• Section: What does this mean for Nvidia?
• Line hint: 627

Context Before

While Ironwood is a proper competitor to Blackwell, Nvidia once again hits back with Vera Rubin. Vera Rubin will deliver huge performance uplifts across compute, memory and network with TPU v8 seeing much smaller improvements.

The 8th generation TPUs will be available in 2027 and will be competing against Nvidia Vera Rubin. There will be 2 versions of TPU v8 but this will be different from the “P” (full) and “E” (lite) SKUs that featured in the then 4th and 5th generations. Rather, it is a dual track with one SKU co-designed with Broadcom (TPU 8AX codenamed “Sunfish”) and one SKU co-designed with MediaTek (TPU 8X codenamed “Zebrafish”).

Evidence

TPU 8AX is very similar to Ironwood, even staying on the same N3E logic node with a similar layout with 2 compute die, 1 I/O chiplet, and 8 stacks of HBM3E.

Context After

TPU v8X only has a single compute die, one I/O die and 6 stacks of HBM3E 12-high. The compute die for TPU v8X will be on N3P, not N3E. The strategy behind Google choosing to partner with MediaTek is to reduce the margin that they pay to their silicon design partners or specifically Broadcom. Broadcom charges Google for the whole System in Package which they stack a healthy margin on. This includes HBM.

This is despite Google being largely responsible for both the front-end and back-end design of the compute elements of the chip, with Broadcom contributing various PHYs (most importantly Broadcom’s best in class SerDes) and controllers. Google wants to move to a model where their silicon partner only charges for the things they add value on and get closer to paying BOM cost for their silicon.

② Atomic Claim

TPU 8AX 延續 N3E，配置 2 compute dies、1 I/O chiplet、8 stacks HBM3E。

• Epistemic Mode: EXPECTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "attribute": "tpu8ax_package",
  "context_nodes": [
    {
      "id": "04_knowledge_base/TSMC N3E",
      "label": "TSMC N3E"
    },
    {
      "id": "04_knowledge_base/Chiplet architecture",
      "label": "Chiplet"
    },
    {
      "id": "04_knowledge_base/HBM3E",
      "label": "HBM3E"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/TPU",
    "label": "TPU"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": "TPU 8AX",
    "numeric_mentions": [
      "2",
      "1",
      "8"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "2",
      "1",
      "8"
    ],
    "value_text": "N3E; 2 compute dies; 1 I/O chiplet; 8 HBM3E stacks"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	TPU	TPU
context_0	TSMC N3E	04_knowledge_base/TSMC N3E
context_1	Chiplet	04_knowledge_base/Chiplet architecture
context_2	HBM3E	HBM3E

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。