clm_737ec6fc2a2c48cdb964ac482f940ebb_r1

2025-11-28_tpuv7-google-takes-a-swing-at-the::TPU7-0023

① SA Source

• Source: 開啟完整 SA 文章
• Section: What does this mean for Nvidia?
• Line hint: 629

Context Before

The 8th generation TPUs will be available in 2027 and will be competing against Nvidia Vera Rubin. There will be 2 versions of TPU v8 but this will be different from the “P” (full) and “E” (lite) SKUs that featured in the then 4th and 5th generations. Rather, it is a dual track with one SKU co-designed with Broadcom (TPU 8AX codenamed “Sunfish”) and one SKU co-designed with MediaTek (TPU 8X codenamed “Zebrafish”).

TPU 8AX is very similar to Ironwood, even staying on the same N3E logic node with a similar layout with 2 compute die, 1 I/O chiplet, and 8 stacks of HBM3E. The memory is upgraded to 12-high stacks from 8-high and with the highest pin speeds of 9.6Gbps from SK Hynix giving it over a ~30% boost in memory bandwidth vs TPU v7.

Evidence

TPU v8X only has a single compute die, one I/O die and 6 stacks of HBM3E 12-high. The compute die for TPU v8X will be on N3P, not N3E.

Context After

This is despite Google being largely responsible for both the front-end and back-end design of the compute elements of the chip, with Broadcom contributing various PHYs (most importantly Broadcom’s best in class SerDes) and controllers. Google wants to move to a model where their silicon partner only charges for the things they add value on and get closer to paying BOM cost for their silicon.

This is where MediaTek comes in who is much more flexible on the custom silicon model. With MediaTek, Google is on the way to moving to a “Customer Owned Tooling” model where the end customer owns and is responsible the entire design end to end. This is the point where custom silicon because truly vertically integrated and the end goal of every hyperscaler. This is ambitious, as it would require the hyperscalers to have full end to end silicon capability like one of major silicon design houses.

② Atomic Claim

TPU v8X 預計採 1 compute die + 1 I/O die + 6 stacks 12-high HBM3E，compute die 使用 N3P。

• Epistemic Mode: EXPECTED
• Mapping Status: PARTIAL

③ Semantic Frame

{
  "attribute": "tpu8x_package",
  "context_nodes": [
    {
      "id": "04_knowledge_base/IO Die",
      "label": "I/O Die"
    },
    {
      "id": "04_knowledge_base/HBM3E",
      "label": "HBM3E"
    },
    {
      "id": "04_knowledge_base/TSMC N3P",
      "label": "TSMC N3P"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/TPU",
    "label": "TPU"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": "TPU v8X",
    "numeric_mentions": [
      "1",
      "1",
      "6",
      "12-high"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "1",
      "1",
      "6",
      "12-high"
    ],
    "value_text": "1 compute die; 1 I/O die; 6 stacks 12-high HBM3E; N3P"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	TPU	TPU
context_0	I/O Die	04_knowledge_base/IO Die
context_1	HBM3E	HBM3E
context_2	TSMC N3P	04_knowledge_base/TSMC N3P

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。