2025-11-28_tpuv7-google-takes-a-swing-at-the::TPU7-0024
① SA Source
- Source: 開啟完整 SA 文章
- Section:
What does this mean for Nvidia? - Line hint:
637
Context Before
This is where MediaTek comes in who is much more flexible on the custom silicon model. With MediaTek, Google is on the way to moving to a “Customer Owned Tooling” model where the end customer owns and is responsible the entire design end to end. This is the point where custom silicon because truly vertically integrated and the end goal of every hyperscaler. This is ambitious, as it would require the hyperscalers to have full end to end silicon capability like one of major silicon design houses.
For TPU V8X, Google was still assisted by MediaTek on the compute side of things with MediaTek owning the tapeout at TSMC and providing their 3nm design libraries to the Google engineering team. Without Broadcom holding their hand, taping out this chip took much longer than expected but this finally happened this quarter.
Evidence
MediaTek’s big design contribution is in the I/O chiplet which features MediaTek’s own 224G SerDes.
Context After
While the big change in TPU V8 is that Google is working with 2 design houses, engineering resources seemed to have been spent adapting to this new model and ramping up their collaboration with MediaTek. We were the first to reveal the dual track approach and have constantly been sending status updates on the TPUv8 projects as it has huge implications for Broadcom and Mediatek in the Accelerator Model. ↗
The result is that the gen-on-gen TPUv8 performance uplifts are much milder relative to what Nvidia plans achieve with Rubin in terms of both compute and memory. For external customers the TCO per effective FLOP advantage remains, but it is much narrower than Ironwood compared to Blackwell.
② Atomic Claim
MediaTek 在 TPU v8X 的主要設計貢獻之一是 I/O chiplet，採其自有 224G SerDes。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "02_companies/MediaTek",
"label": "MediaTek"
},
"role": "partner"
},
{
"node": {
"id": "04_knowledge_base/Chiplet architecture",
"label": "I/O chiplet"
},
"role": "component"
},
{
"node": {
"id": "04_knowledge_base/SerDes",
"label": "SerDes"
},
"role": "technology"
}
],
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"224G"
],
"temporal_mentions": []
},
"relation_type": "TPUV8X_MEDIATEK_IO_CONTRIBUTION"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| partner | MediaTek | MediaTek |
| component | I/O chiplet | 04_knowledge_base/Chiplet architecture |
| technology | SerDes | SerDes |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。