2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0028
① SA Source
- Source: 開啟完整 SA 文章
- Section:
The Revolutionary Changes Coming with HBM4 - Line hint:
263
Context Before
HBM4 is where there will be more drastic changes to the HBM architecture on many facets: bus width, form factor and customization vs. “standard” off-the-shelf HBM.
HBM is high bandwidth because it has a much wider memory bus of 1024 bits compared to other forms of DRAM with 64 bits (16x the I/O). The bus of a single stack consists of multiple channels on each of the HBM core die. Currently, the bus for HBM3 and HBM3E is divided into sixteen 64-bit channels, with two nearly independent pseudo-channels per channel.
Evidence
Context After
Source: SK Hynix
② Atomic Claim
JEDEC 初步 HBM4 規格為最高 6.4Gbps、約 1.6TB/s，約為 HBM3E peak bandwidth 的 1.5 倍。
- Epistemic Mode:
ATTRIBUTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "HBM4 up to 1.6TB/s at 6.4Gbps vs HBM3E 9.2Gbps peak",
"entities": [
{
"id": "04_knowledge_base/HBM4",
"label": "HBM4"
},
{
"id": "04_knowledge_base/HBM3E",
"label": "HBM3E"
},
{
"id": "04_knowledge_base/JEDEC",
"label": "JEDEC"
}
],
"frame_type": "COMPARISON",
"metric": "peak_memory_bandwidth",
"operator": "ABOUT_1_5X",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"6.4Gbps",
"1.6TB/s",
"1.5x",
"9.2Gbps"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | HBM4 | HBM4 |
| comparison_entity_1 | HBM3E | HBM3E |
| comparison_entity_2 | JEDEC | JEDEC |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。