2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0008
① SA Source
- Source: 開啟完整 SA 文章
- Section:
HBM Primer - Line hint:
43
Context Before
The implication of having much more I/O is increased routing density and complexity. Each I/O requires an individual wire/trace, with additional wiring required for power and control. For a HBM3E stack, there are over a 1,000 wires between the adjacent XPU and the HBM. This level of routing density is not achievable on a PCB or package substrate; therefore, an interposer (silicon or organic) in a 2.5D package assembly like CoWoS is required.
To reduce latency and energy consumption for data transfer, HBM needs to be placed directly adjacent to the shoreline of the compute engine. This makes shoreline (the edge of a SOC) more valuable as HBM can only be limited to the 2 edges of the SOC with the other 2 edges reserved for I/O off the package. This limits the area HBM can be placed in and requires vertical stacking of memory die to provide enough capacity.
Evidence
Context After
The other difference is at the back-end, where the HBM needs to be stacked to 9 or 13 layers in total (8/12 DRAM layers on top of a logic base die at the bottom). Along with CoWoS, HBM has brought packaging technology to the mainstream. Niche packaging technologies like MR-MUF have now become common knowledge for industry participants.
Explosive Bit Demand
② Atomic Claim
SK Hynix D1z DDR4 bit density 為 0.296 Gb/mm²，比 HBM3 的 0.16 Gb/mm² 高 85%。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "DDR4 0.296 Gb/mm2 vs HBM3 0.16 Gb/mm2",
"entities": [
{
"id": "04_knowledge_base/DDR4",
"label": "DDR4"
},
{
"id": "04_knowledge_base/HBM3",
"label": "HBM3"
},
{
"id": "02_companies/000660",
"label": "SK Hynix"
}
],
"frame_type": "COMPARISON",
"metric": "bit_density",
"operator": "DDR4_85_PERCENT_HIGHER",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"0.296 Gb/mm2",
"85%",
"0.16 Gb/mm2"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | DDR4 | DDR4 |
| comparison_entity_1 | HBM3 | HBM3 |
| comparison_entity_2 | SK Hynix | 000660 |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。