clm_c6e9f59e7d2044d6a67e6ff94abc8a85_r1

2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0021

① SA Source

• Source: 開啟完整 SA 文章
• Section: Process Flow: Yields
• Line hint: 85

Context Before

HBM is a more technically sophisticated product than other DRAM form factors, especially given the high 3DIC stack. As such, packaging yields are not going to be comparable to what manufacturers are accustomed to compared to their more conventional products. However, yields at the front end are also challenging, and we think yield is more of a problem at the front end. As mentioned above, HBM is not demanding with regards to speed bins, so why is this the case?

The reason goes back to the 3DIC assembly and the TSVs. One of the challenges is the Power Distribution Network (PDN) with the TSVs needing to be able to deliver power up the stack. TSV layout and design is proprietary and one of the main areas of differentiation between the various manufacturers.

Evidence

Hynix’s HBM3E has reduced peripheral area and introduced all-around power TSVs on the die instead of having two banks of power TSVs, thereby increasing the number of TSVs by almost 6x. As a result, SKH has achieved a much lower IR drop, up to 75% lower for VPP.

Context After

Similarly, Micron’s surprising leapfrog in HBM technology (Micron didn’t even offer standard HBM3) was due to its focus on TSVs and the power delivery network. The TSV network seems likely to be the point of differentiation that allows Micron to claim 30% lower power consumption, though that claim is yet to be verified.

② Atomic Claim

Hynix HBM3E 採 all-around power TSV，使 TSV 數量接近增加 6 倍，VPP IR drop 最多降低 75%。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "power_tsv_design",
  "context_nodes": [
    {
      "id": "02_companies/000660",
      "label": "Hynix"
    },
    {
      "id": "04_knowledge_base/TSV",
      "label": "TSV"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/HBM3E",
    "label": "HBM3E"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "6x",
      "75%"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "6x",
      "75%"
    ],
    "value_text": "all-around power TSVs; ~6x TSV count; VPP IR drop up to 75% lower"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	HBM3E	HBM3E
context_0	Hynix	000660
context_1	TSV	TSV

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。