clm_c45a73a6c36d4d6cb907af295863d1e4_r1

2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0013

① SA Source

• Source: 開啟完整 SA 文章
• Section: Process Flow: Front End
• Line hint: 57

Context Before

Source: SemiAnalysis

Process Flow: Front End

Evidence

When regular DDR DRAM capacity “converts” to HBM capacity – the main change is the addition of tools for forming the TSVs, and more bumping capacity as HBM wafers are bumped on both sides.

Context After

TSVs require etchers to create the vias, and deposition and plating tools to fill them. To reveal the TSVs, grinders, another etch step, and temporary bonders to attach carrier wafers used in this process are required. This is why HBM capacity is now quoted in terms of TSV capacity, as this is the main incremental set of processes that turn DDR wafers into HBM wafers.

For bumping, this is mainly deposition, plating and stripping. Also, optical inspection tools from Camtek and Onto are available to check that the bumps are not defective and are of the correct profile.

② Atomic Claim

DDR DRAM capacity 轉成 HBM capacity 的主要新增製程是 TSV tooling 與更多 bumping capacity；HBM wafers 需要雙面 bumping。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "frame_type": "NARY_RELATION",
  "participants": [
    {
      "node": {
        "id": "04_knowledge_base/DDR",
        "label": "DDR"
      },
      "role": "source_memory"
    },
    {
      "node": {
        "id": "04_knowledge_base/HBM",
        "label": "HBM"
      },
      "role": "target_memory"
    },
    {
      "node": {
        "id": "04_knowledge_base/TSV",
        "label": "TSV"
      },
      "role": "process"
    },
    {
      "node": {
        "id": "04_knowledge_base/Bumping",
        "label": "Bumping"
      },
      "role": "process"
    }
  ],
  "qualifiers": {
    "condition_text": "HBM wafers bumped on both sides",
    "numeric_mentions": [],
    "temporal_mentions": []
  },
  "relation_type": "HBM_CAPACITY_CONVERSION_PROCESS"
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
source_memory	DDR	DDR
target_memory	HBM	HBM
process	TSV	TSV
process	Bumping	Bumping

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。