2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0027
① SA Source
- Source: 開啟完整 SA 文章
- Section:
The Revolutionary Changes Coming with HBM4 - Line hint:
263
Context Before
HBM4 is where there will be more drastic changes to the HBM architecture on many facets: bus width, form factor and customization vs. “standard” off-the-shelf HBM.
HBM is high bandwidth because it has a much wider memory bus of 1024 bits compared to other forms of DRAM with 64 bits (16x the I/O). The bus of a single stack consists of multiple channels on each of the HBM core die. Currently, the bus for HBM3 and HBM3E is divided into sixteen 64-bit channels, with two nearly independent pseudo-channels per channel.
Evidence
The big change for HBM4 is that the bus width will double to 2048-bit wide from the 1024-bit bus. Memory manufacturers will be relying more on the wider bus to drive up bandwidth rather than increasing pin speeds.
Context After
Source: SK Hynix
② Atomic Claim
HBM4 bus width 將由 1,024-bit 加倍至 2,048-bit，memory vendors 更依賴 wider bus 而非提高 pin speed 來增加 bandwidth。
- Epistemic Mode:
EXPECTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"attribute": "bus_width",
"context_nodes": [],
"entity": {
"id": "04_knowledge_base/HBM4",
"label": "HBM4"
},
"frame_type": "ATTRIBUTE",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"2048-bit",
"1024-bit"
],
"temporal_mentions": []
},
"value": {
"numeric_mentions": [
"2048-bit",
"1024-bit"
],
"value_text": "2048-bit vs 1024-bit prior generation"
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| entity | HBM4 | HBM4 |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。