2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0004
① SA Source
- Source: 開啟完整 SA 文章
- Section:
HBM Primer - Line hint:
39
Context Before
Source: SemiAnalysis
Evidence
For a HBM3E stack, there are over a 1,000 wires between the adjacent XPU and the HBM. This level of routing density is not achievable on a PCB or package substrate; therefore, an interposer (silicon or organic) in a 2.5D package assembly like CoWoS is required.
Context After
To reduce latency and energy consumption for data transfer, HBM needs to be placed directly adjacent to the shoreline of the compute engine. This makes shoreline (the edge of a SOC) more valuable as HBM can only be limited to the 2 edges of the SOC with the other 2 edges reserved for I/O off the package. This limits the area HBM can be placed in and requires vertical stacking of memory die to provide enough capacity.
To enable the 3DIC form factor, each layer of the stack needs to have TSVs (excluding the top of stack) that can deliver power and signal to the layer above. The additional area required to fit these TSVs is what makes HBM die sizes larger than their DDR equivalent: SK Hynix D1z DDR4 has a bit density of 0.296 Gb/mm2, 85% more dense than their HBM3 which is 0.16 Gb/mm2. This TSV process is one of the key differences between standard DRAM, and tooling for this is the main bottleneck when it comes to converting regular DDR DRAM wafer capacity to HBM capacity.
② Atomic Claim
HBM3E 與相鄰 XPU 之間超過 1,000 條 wires，routing density 高到需要 interposer / 2.5D package（如 CoWoS），無法只靠 PCB 或 substrate。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"frame_type": "NARY_RELATION",
"participants": [
{
"node": {
"id": "04_knowledge_base/HBM3E",
"label": "HBM3E"
},
"role": "memory"
},
{
"node": {
"id": "04_knowledge_base/XPU",
"label": "XPU"
},
"role": "compute"
},
{
"node": {
"id": "04_knowledge_base/Interposer",
"label": "Interposer"
},
"role": "interposer"
},
{
"node": {
"id": "04_knowledge_base/CoWoS",
"label": "CoWoS"
},
"role": "package"
}
],
"qualifiers": {
"condition_text": "routing density not achievable on PCB/package substrate",
"numeric_mentions": [
"1,000"
],
"temporal_mentions": []
},
"relation_type": "ROUTING_DENSITY_REQUIRES_2_5D"
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| memory | HBM3E | HBM3E |
| compute | XPU | XPU |
| interposer | Interposer | Interposer |
| package | CoWoS | CoWoS |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。