2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0033
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Getting Down to the Wire: Better PHYs - Line hint:
293
Context Before
Getting Down to the Wire: Better PHYs
At the heart of the problems with the current base die design is the PHY that interfaces with the host. HBM uses a standard DDR PHY using planar transistors fabricated on a DRAM process. These lower performance transistors hamper the signaling capability of PHY so that signals can only be fixed and unidirectional at slow speeds.
Evidence
Context After
Companies like Eliyan are publicly pitching their NuLink interconnect for a role in HBM4 base dies, so there may be multiple options. We can reasonably see UCIe as the baseline improvement likely to be delivered, since it has already proven that 10x better beachfronts can be in production.
Marvell is the first company to reveal their custom HBM base die solution with the main improvement via implementing a D2D PHY that uses only 1/4 of the shoreline, freeing up silicon for other uses.
② Atomic Claim
UCIe bandwidth density 約 10Tbps/mm,約為 HBM3E ~0.7Tbps/mm beachfront efficiency 的 15 倍,且 energy/bit 更低。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "UCIe 10 Tbps/mm vs HBM3E ~0.7 Tbps/mm",
"entities": [
{
"id": "04_knowledge_base/UCIe",
"label": "UCIe"
},
{
"id": "04_knowledge_base/HBM3E",
"label": "HBM3E"
}
],
"frame_type": "COMPARISON",
"metric": "bandwidth_density",
"operator": "ABOUT_15X",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [
"10 Tbps/mm",
"15x",
"0.7 Tbps/mm"
],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
⑤ Human Review
請在 Properties 逐項確認:
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。