2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0035
① SA Source
- Source: 開啟完整 SA 文章
- Section:
Economics and Supply Chain Implications - Line hint:
423
Context Before
What about hyperscaler ASICs? Hyperscalers need to keep up with the best merchant GPUs so they will also need to make the most of this functionality though the degree of adoption will vary. For example, Google builds systems with more focus on reliability and their TPU design philosophy reflects that with silicon choices not being aggressive to sidestep the high failure rates that plague chip designs that redline performance so they will not be aggressive on things like compute in base die.
This one more feature that ASIC designers will need to rely on their custom silicon partners to design the suite of the features above that best complement the architecture of each ASIC program. We can add HBM base dies as another surface area where design partners can add value in their ASIC designs. The other option would be to assemble various off-the-shelf IP blocks to create the custom base die functionality they want, for example using Eliyan’s UMI as an all-in-one PHY for beachfront expansion.
Evidence
The other interesting element is custom base dies strengthen lock-in for memory vendor. Each HBM vendor has their own proprietary TSV layouts (see above) so each custom base die will need to be configured to match a respective memory vendor’s TSV layout: a custom base die designed for Micron HBM4E won’t be compatible with SK Hynix HBM4E.
Context After
On the flip side this makes life even more difficult for memory vendors who are behind on their roadmaps like Samsung. Customers would not want to undergo the extra effort and investment to tape out base die designs compatible with Samsung given the understandable concerns around whether Samsung is on track to deliver competitive HBM4 and beyond.
For once, these memory vendors can have something resembling that of customer switching costs.
② Atomic Claim
Custom base die 會強化 memory-vendor lock-in，因各 HBM vendor 的 proprietary TSV layout 不同；為 Micron HBM4E 設計的 base die 不相容於 SK Hynix HBM4E。
- Epistemic Mode:
ASSERTED - Mapping Status:
COMPLETE
③ Semantic Frame
{
"comparison_expression": "custom base die must match vendor-specific TSV layout",
"entities": [
{
"id": "02_companies/MU",
"label": "Micron"
},
{
"id": "02_companies/000660",
"label": "SK Hynix"
},
{
"id": "04_knowledge_base/Custom Base Die",
"label": "Custom Base Die"
},
{
"id": "04_knowledge_base/HBM4E",
"label": "HBM4E"
}
],
"frame_type": "COMPARISON",
"metric": "base_die_compatibility",
"operator": "NOT_COMPATIBLE_ACROSS_VENDOR",
"qualifiers": {
"condition_text": null,
"numeric_mentions": [],
"temporal_mentions": []
}
}④ Canonical Entity Mapping
| Role | Surface Label | Canonical Target |
|---|---|---|
| comparison_entity_0 | Micron | MU |
| comparison_entity_1 | SK Hynix | 000660 |
| comparison_entity_2 | Custom Base Die | 04_knowledge_base/Custom Base Die |
| comparison_entity_3 | HBM4E | HBM4E |
⑤ Human Review
請在 Properties 逐項確認：
- 原文 → Atomic Claim 是否忠實
- Atomic Claim → Semantic Frame 是否忠實
- Canonical Entity mapping 是否正確
- Epistemic mode 是否保留原文語氣
- 最後選擇
review_action
Review state
Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。