clm_0d369d4a03664c17bd9680c22110e5e2_r1

2025-08-12_scaling-the-memory-wall-the-rise-and-roadmap-of-hbm::HBM25-0034

① SA Source

• Source: 開啟完整 SA 文章
• Section: Getting Down to the Wire: Better PHYs
• Line hint: 303

Context Before

Hynix’s HBM3E base die. Source: SK Hynix

Evidence

Currently HBM3E expends 95% of energy per bit on moving the data and the I/O interface, and less than 5% into reading or writing values in the DRAM.

Context After

These improvements have been discussed for a long time in DRAM forums such as JEDEC but generally blocked by the slow performance of the transistors on DRAM chips. The vendors quite reasonably want to stick with the DDR style interface where they have 30 years’ experience of implementing it despite transistor limitations. However, when the base chip is in play those limitations no longer apply. The base chip might be in a reduced cost version of an advanced logic process like 5nm where clearly the advanced PHY options are all available.

Moreover, the base chip is situated right under the TSVs which total a fraction of a mm in height, a very short distance for a PHY to bridge. It should be possible for signaling systems at higher frequencies even with DRAM-process transistors, like the proven GDDR use of bit rates up to 32 Gbps, to drive faster data at much lower energy per bit over these short distances. There are some issues here in signal quality for TSVs in a tall stack, but clearly an incentive to find improvements that leverage a smart, modern base chip. HBM4 will be a phase change in how we look at connecting to DRAM.

② Atomic Claim

HBM3E 每 bit energy 約 95% 用於 data movement/I/O，不到 5% 用於 DRAM read/write。

• Epistemic Mode: ASSERTED
• Mapping Status: COMPLETE

③ Semantic Frame

{
  "attribute": "energy_per_bit_breakdown",
  "context_nodes": [
    {
      "id": "04_knowledge_base/DRAM",
      "label": "DRAM"
    }
  ],
  "entity": {
    "id": "04_knowledge_base/HBM3E",
    "label": "HBM3E"
  },
  "frame_type": "ATTRIBUTE",
  "qualifiers": {
    "condition_text": null,
    "numeric_mentions": [
      "95%",
      "5%"
    ],
    "temporal_mentions": []
  },
  "value": {
    "numeric_mentions": [
      "95%",
      "5%"
    ],
    "value_text": "~95% movement/I/O; <5% DRAM read/write"
  }
}

④ Canonical Entity Mapping

Role	Surface Label	Canonical Target
entity	HBM3E	HBM3E
context_0	DRAM	DRAM

⑤ Human Review

請在 Properties 逐項確認：

• 原文 → Atomic Claim 是否忠實
• Atomic Claim → Semantic Frame 是否忠實
• Canonical Entity mapping 是否正確
• Epistemic mode 是否保留原文語氣
• 最後選擇 review_action

Review state

Markdown 內文不是正式 approval。只有 Apply bridge 寫入的 Decision Ledger event 才是正式決策。