| 04_knowledge_base/RTL | 44 |
| 04_knowledge_base/IC design verification | 37 |
| 03_industries/Foundry | 35 |
| 04_knowledge_base/Transistor | 33 |
| 02_companies/SNPS | 32 |
| 04_knowledge_base/Electronic Design Automation | 30 |
| 04_knowledge_base/PDK | 27 |
| 04_knowledge_base/Standard cell | 27 |
| 02_companies/INTC | 20 |
| 02_companies/Cadence Design Systems | 20 |
| 04_knowledge_base/Semiconductor Physical Design | 14 |
| 04_knowledge_base/CPU | 13 |
| 02_companies/2330 台積電 | 12 |
| 04_knowledge_base/Semiconductor PPA | 10 |
| 04_knowledge_base/GDSII | 10 |
| 04_knowledge_base/Design Signoff | 9 |
| 04_knowledge_base/Design Rule | 9 |
| 04_knowledge_base/Tapeout | 8 |
| 04_knowledge_base/FPGA | 8 |
| 02_companies/Together AI | 8 |
| 02_companies/NVDA | 7 |
| 04_knowledge_base/Place and Route | 7 |
| 04_knowledge_base/SoC | 6 |
| 02_companies/AMD | 6 |
| 04_knowledge_base/DTCO | 6 |
| 04_knowledge_base/PVT corners | 6 |
| 04_knowledge_base/Intel 18A | 6 |
| 04_knowledge_base/STCO | 6 |
| 04_knowledge_base/Semiconductor Fab | 6 |
| 02_companies/AAPL | 5 |
| 04_knowledge_base/矽晶圓 | 5 |
| 02_companies/GOOG | 5 |
| 04_knowledge_base/Semiconductor Physical Verification | 5 |
| 04_knowledge_base/SRAM | 5 |
| 04_knowledge_base/Logic Synthesis | 5 |
| 04_knowledge_base/封裝 | 4 |
| 04_knowledge_base/AWS | 4 |
| 04_knowledge_base/GPU | 4 |
| 04_knowledge_base/AI Accelerator | 4 |
| 04_knowledge_base/微影製程 | 4 |
| 04_knowledge_base/Equivalence Checking | 4 |
| 04_knowledge_base/Cadence Palladium | 4 |
| 02_companies/Siemens EDA | 4 |
| 04_knowledge_base/SystemVerilog | 4 |
| 04_knowledge_base/FinFLEX | 4 |
| 04_knowledge_base/Photomask Set | 4 |
| 04_knowledge_base/Synopsys Sentaurus | 4 |
| 04_knowledge_base/TCAD | 4 |
| 04_knowledge_base/ATE | 3 |
| 04_knowledge_base/ZeBu | 3 |
| 04_knowledge_base/Chiplet architecture | 3 |
| 04_knowledge_base/Synopsys PrimeTime | 3 |
| 04_knowledge_base/HTOL | 3 |
| 02_companies/Switch | 3 |
| 04_knowledge_base/Interconnect Stack | 3 |
| 04_knowledge_base/Power Delivery Network | 3 |
| 04_knowledge_base/PMOS | 3 |
| 04_knowledge_base/NMOS | 3 |
| 04_knowledge_base/Coverage closure | 3 |
| 04_knowledge_base/TPU | 2 |
| 04_knowledge_base/探針卡 | 2 |
| 04_knowledge_base/CoWoS | 2 |
| 04_knowledge_base/HBM | 2 |
| 04_knowledge_base/EMIB | 2 |
| 04_knowledge_base/SLT | 2 |
| 04_knowledge_base/Frozen | 2 |
| 04_knowledge_base/PCIe | 2 |
| 04_knowledge_base/Burn-in | 2 |
| 04_knowledge_base/Shift-Left Design Verification | 2 |
| 04_knowledge_base/Design Space Exploration | 2 |
| 04_knowledge_base/Yield Harvesting | 2 |
| 04_knowledge_base/Moore’s Law | 2 |
| 02_companies/Arm Holdings | 2 |
| 04_knowledge_base/AMD Instinct MI455X | 2 |
| 04_knowledge_base/Verilog | 2 |
| 04_knowledge_base/Fusion Compiler | 2 |
| 02_companies/Mentor Graphics | 2 |
| 04_knowledge_base/Critical Path | 2 |
| 04_knowledge_base/Engineering Change Order | 2 |
| 04_knowledge_base/Cadence Genus | 2 |
| 04_knowledge_base/Design Compiler | 2 |
| 04_knowledge_base/Contact | 2 |
| 04_knowledge_base/Via | 2 |
| 04_knowledge_base/Process node | 2 |
| 04_knowledge_base/Cadence Innovus | 2 |
| 04_knowledge_base/Synopsys IC Compiler II | 2 |
| 04_knowledge_base/Backside Power Delivery | 2 |
| 04_knowledge_base/Functional coverage | 2 |
| 04_knowledge_base/NanoFlex | 2 |
| 04_knowledge_base/IP block | 2 |
| 02_companies/Advantest | 1 |
| 02_companies/AVGO | 1 |
| 04_knowledge_base/ASIC | 1 |
| 02_companies/2454 聯發科 | 1 |
| 04_knowledge_base/FT | 1 |
| 04_knowledge_base/AOI | 1 |
| 04_knowledge_base/N2 | 1 |
| 02_companies/TER | 1 |
| 02_companies/MSFT | 1 |
| 04_knowledge_base/Hyperscaler | 1 |
| 04_knowledge_base/NAND Flash | 1 |
| 02_companies/MediaTek | 1 |
| 04_knowledge_base/A16 | 1 |
| 04_knowledge_base/Siemens Calibre | 1 |
| 04_knowledge_base/MBIST | 1 |
| 04_knowledge_base/JTAG | 1 |
| 04_knowledge_base/PPACt | 1 |
| 04_knowledge_base/Network on Chip | 1 |
| 04_knowledge_base/Heterogeneous integration | 1 |
| 02_companies/GlobalFoundries | 1 |
| 04_knowledge_base/Foveros | 1 |
| 04_knowledge_base/Ion Implantation | 1 |
| 02_companies/Keysight | 1 |
| 04_knowledge_base/VC SpyGlass | 1 |
| 04_knowledge_base/Ruthenium | 1 |
| 02_companies/GitHub | 1 |
| 04_knowledge_base/VC Formal | 1 |
| 03_industries/SaaS產業 | 1 |
| 04_knowledge_base/Synopsys Formality | 1 |
| 04_knowledge_base/Hardware emulation | 1 |
| 04_knowledge_base/DSO.ai | 1 |
| 04_knowledge_base/Silicon bridge | 1 |
| 04_knowledge_base/Sapphire Rapids | 1 |
| 04_knowledge_base/Instruction Set Architecture | 1 |
| 04_knowledge_base/Non-Equilibrium Green’s Function | 1 |
| 04_knowledge_base/BSIM-CMG | 1 |
| 04_knowledge_base/JasperGold | 1 |
| 04_knowledge_base/Design Verification | 1 |
| 02_companies/Apollo Global Management | 1 |
| 04_knowledge_base/SerDes | 1 |
| 04_knowledge_base/JEDEC | 1 |
| 04_knowledge_base/Computer-Aided Engineering | 1 |
| 04_knowledge_base/AMBA CHI | 1 |
| 04_knowledge_base/Conformal LEC | 1 |
| 04_knowledge_base/Synopsys VCS | 1 |
| 04_knowledge_base/Constrained random verification | 1 |
| 04_knowledge_base/Nanosheet | 1 |
| 02_companies/Xilinx | 1 |
| 04_knowledge_base/Timing closure | 1 |
| 04_knowledge_base/AMD EPYC Turin | 1 |
| 04_knowledge_base/Density Functional Theory | 1 |
| 04_knowledge_base/Universal Verification Methodology | 1 |
| 04_knowledge_base/OpenROAD | 1 |
| 04_knowledge_base/GB10 | 1 |
| 04_knowledge_base/Attention Feed Forward Network Disaggregation | 1 |
| 04_knowledge_base/Microsoft Azure | 1 |
| 04_knowledge_base/CFET | 1 |
| 04_knowledge_base/DesignWare | 1 |
| 04_knowledge_base/Questa | 1 |
| 04_knowledge_base/Xcelium | 1 |
| 04_knowledge_base/Semiconductor manufacturing | 1 |
| 04_knowledge_base/Copper | 1 |
| 02_companies/Handshake (AI Data Company) | 1 |
| 04_knowledge_base/Hybrid Bonding | 1 |
| 04_knowledge_base/Nitro | 1 |
| 04_knowledge_base/Trainium | 1 |
| 02_companies/DeepMind | 1 |
| 02_companies/IBM | 1 |
| 04_knowledge_base/Flip-Flop | 1 |
| 04_knowledge_base/Electrical Rule Check | 1 |
| 04_knowledge_base/RedHawk-SC | 1 |
| 04_knowledge_base/Automatic Test Pattern Generation | 1 |
| 04_knowledge_base/Power rail | 1 |
| 04_knowledge_base/Inductor | 1 |
| 04_knowledge_base/iSpatial | 1 |
| 04_knowledge_base/Optical Proximity Correction | 1 |
| 04_knowledge_base/SystemVerilog Assertions | 1 |
| 04_knowledge_base/Reticle | 1 |
| 04_knowledge_base/Granite Rapids | 1 |
| 04_knowledge_base/Logic Process | 1 |
| 04_knowledge_base/Engineering Sample | 1 |
| 04_knowledge_base/Cadence Tempus | 1 |
| 04_knowledge_base/Code coverage | 1 |
| 04_knowledge_base/Intel Ponte Vecchio | 1 |
| 04_knowledge_base/Tensor Core | 1 |
| 04_knowledge_base/3nm | 1 |
| 04_knowledge_base/Finite State Machine | 1 |
| 04_knowledge_base/2nm | 1 |
| 04_knowledge_base/QuantumATK | 1 |
| 04_knowledge_base/Final Test | 1 |
| 04_knowledge_base/Capacitor | 1 |
| 04_knowledge_base/Gate-All-Around | 1 |
| 04_knowledge_base/Thin-film deposition | 1 |
| 04_knowledge_base/Library Exchange Format | 1 |
| 04_knowledge_base/Etching | 1 |
| 04_knowledge_base/Synopsys Design Vision | 1 |
| 04_knowledge_base/Metallization | 1 |
| 04_knowledge_base/DDR | 1 |
| 04_knowledge_base/Hold time | 1 |
| 04_knowledge_base/Covergroup | 1 |
| 04_knowledge_base/Synopsys IC Validator | 1 |
| 04_knowledge_base/Design for Test | 1 |
| 04_knowledge_base/Post-silicon validation | 1 |
| 04_knowledge_base/Setup Time | 1 |
| 04_knowledge_base/Voltus | 1 |
| 04_knowledge_base/Design Rule Check | 1 |