2023-12-11_asml-dilemma-high-na-euv-is-worse
Canonical Target Counts
| Target | Occurrences |
|---|
| 04_knowledge_base/EUV | 26 |
| 02_companies/ASML | 25 |
| 04_knowledge_base/微影製程 | 23 |
| 04_knowledge_base/矽晶圓 | 5 |
| 04_knowledge_base/Double Patterning | 5 |
| 04_knowledge_base/3nm | 5 |
| 04_knowledge_base/DUV | 4 |
| 04_knowledge_base/DRAM | 4 |
| 04_knowledge_base/Photomask | 4 |
| 02_companies/MU | 3 |
| 04_knowledge_base/Overlay | 3 |
| 04_knowledge_base/Semiconductor Fab | 3 |
| 04_knowledge_base/Photoresist | 3 |
| 04_knowledge_base/Chiplet architecture | 2 |
| 04_knowledge_base/Numerical Aperture | 2 |
| 02_companies/Aligned Data Centers | 1 |
| 02_companies/INTC | 1 |
| 02_companies/NVDA | 1 |
| 04_knowledge_base/Sapphire Rapids | 1 |
| 04_knowledge_base/Multi-Chip Module | 1 |
| 04_knowledge_base/Intel 14A process node | 1 |
| 04_knowledge_base/MI300 | 1 |
| 04_knowledge_base/Electronic Design Automation | 1 |
| 04_knowledge_base/H100 | 1 |
| 02_companies/AMD | 1 |
| 02_companies/000660 | 1 |
| 04_knowledge_base/Critical dimension | 1 |
| 04_knowledge_base/Multi-Patterning | 1 |
| 04_knowledge_base/Process node | 1 |
| 04_knowledge_base/Design Rule | 1 |
| 04_knowledge_base/Mask Writer | 1 |
| 04_knowledge_base/Compute Tile | 1 |
| 03_industries/WFE | 1 |
| 04_knowledge_base/Rayleigh Criterion | 1 |
| 04_knowledge_base/Transistor | 1 |
| 04_knowledge_base/Reticle | 1 |
| 04_knowledge_base/2nm | 1 |