| 04_knowledge_base/Zen 4c | 43 |
| 04_knowledge_base/AMD EPYC Bergamo | 37 |
| 02_companies/AMD | 33 |
| 04_knowledge_base/Zen 4 | 28 |
| 04_knowledge_base/AMD EPYC Genoa | 18 |
| 04_knowledge_base/Core Compute Die | 16 |
| 04_knowledge_base/CPU | 16 |
| 02_companies/INTC | 12 |
| 04_knowledge_base/EPYC | 10 |
| 04_knowledge_base/Standard cell | 10 |
| 04_knowledge_base/SRAM | 9 |
| 02_companies/Arm Holdings | 7 |
| 04_knowledge_base/AMD Core Complex | 6 |
| 04_knowledge_base/Hyperscaler | 6 |
| 04_knowledge_base/IO Die | 6 |
| 02_companies/2330 台積電 | 5 |
| 04_knowledge_base/GMI3 | 5 |
| 04_knowledge_base/Transistor | 5 |
| 04_knowledge_base/5nm | 5 |
| 04_knowledge_base/x86 | 5 |
| 04_knowledge_base/Semiconductor Physical Design | 4 |
| 04_knowledge_base/Semiconductor PPA | 4 |
| 04_knowledge_base/L3 cache | 4 |
| 04_knowledge_base/Moore’s Law | 3 |
| 02_companies/GOOG | 3 |
| 02_companies/MSFT | 3 |
| 04_knowledge_base/Zen 5c | 3 |
| 04_knowledge_base/Sierra Forest | 3 |
| 04_knowledge_base/AMD EPYC Rome | 2 |
| 04_knowledge_base/DDR5 | 2 |
| 04_knowledge_base/基板 | 2 |
| 02_companies/Together AI | 2 |
| 04_knowledge_base/PCIe | 2 |
| 04_knowledge_base/TSV | 2 |
| 04_knowledge_base/Chiplet architecture | 2 |
| 04_knowledge_base/ARM Phoenix CPU | 2 |
| 04_knowledge_base/RTL | 2 |
| 02_companies/IBM | 2 |
| 04_knowledge_base/Datacenter CPU | 2 |
| 04_knowledge_base/AMD EPYC Turin | 2 |
| 04_knowledge_base/TSMC N5 | 2 |
| 02_companies/Amazon | 2 |
| 04_knowledge_base/L2 cache | 2 |
| 04_knowledge_base/Pump | 2 |
| 04_knowledge_base/SP5 | 2 |
| 02_companies/Ampere Computing | 1 |
| 04_knowledge_base/TSMC N3E | 1 |
| 04_knowledge_base/AMD EPYC Milan | 1 |
| 04_knowledge_base/Clearwater Forest | 1 |
| 02_companies/AAPL | 1 |
| 04_knowledge_base/Timing closure | 1 |
| 04_knowledge_base/PowerVia | 1 |
| 04_knowledge_base/SoC | 1 |
| 04_knowledge_base/Zen 6 | 1 |
| 04_knowledge_base/Instruction Set Architecture | 1 |
| 04_knowledge_base/Granite Rapids | 1 |
| 04_knowledge_base/Contact | 1 |
| 04_knowledge_base/Wafer Pricing | 1 |
| 04_knowledge_base/Thermal Design Power | 1 |
| 04_knowledge_base/ASIC | 1 |
| 04_knowledge_base/Wordline | 1 |
| 04_knowledge_base/3D V-Cache | 1 |
| 04_knowledge_base/7nm | 1 |
| 04_knowledge_base/Backside Power Delivery | 1 |
| 04_knowledge_base/Design Rule | 1 |
| 04_knowledge_base/Scribe line | 1 |
| 04_knowledge_base/Merchant Silicon | 1 |
| 04_knowledge_base/FinFLEX | 1 |
| 04_knowledge_base/3nm | 1 |
| 04_knowledge_base/FinFET | 1 |
| 04_knowledge_base/CMOS | 1 |
| 04_knowledge_base/Memory Bandwidth per Core | 1 |
| 04_knowledge_base/14nm | 1 |
| 04_knowledge_base/AmpereOne | 1 |
| 04_knowledge_base/Cortex-X2 | 1 |
| 04_knowledge_base/Neoverse V1 | 1 |
| 04_knowledge_base/Crestmont | 1 |
| 04_knowledge_base/Infinity Fabric on Package | 1 |
| 04_knowledge_base/Cost per Transistor | 1 |
| 04_knowledge_base/GPU | 1 |
| 04_knowledge_base/AVX-512 | 1 |
| 04_knowledge_base/Bitline | 1 |