2023-05-03_intel-emerald-rapids-backtracks-on
Canonical Target Counts
| Target | Occurrences |
|---|
| 02_companies/INTC | 27 |
| 04_knowledge_base/NUMA | 27 |
| 04_knowledge_base/Chiplet architecture | 22 |
| 04_knowledge_base/CPU | 10 |
| 04_knowledge_base/L3 cache | 10 |
| 04_knowledge_base/Sapphire Rapids | 9 |
| 04_knowledge_base/Emerald Rapids | 7 |
| 04_knowledge_base/Semiconductor Physical Design | 5 |
| 02_companies/AMD | 4 |
| 04_knowledge_base/PCIe | 3 |
| 04_knowledge_base/Set associativity | 3 |
| 04_knowledge_base/EMR-XCC | 3 |
| 04_knowledge_base/DDR5 | 2 |
| 04_knowledge_base/SRAM | 2 |
| 02_companies/NVDA | 2 |
| 04_knowledge_base/LGA 4677 | 2 |
| 04_knowledge_base/Cache line | 2 |
| 04_knowledge_base/Eagle Stream | 1 |
| 02_companies/GOOG | 1 |
| 02_companies/Baidu | 1 |
| 04_knowledge_base/CXL | 1 |
| 02_companies/Amazon | 1 |
| 04_knowledge_base/Semiconductor Chip Binning | 1 |
| 04_knowledge_base/封裝 | 1 |
| 02_companies/Ampere Computing | 1 |
| 02_companies/Together AI | 1 |
| 04_knowledge_base/Silicon bridge | 1 |
| 02_companies/META | 1 |
| 04_knowledge_base/Intel Ultra Path Interconnect (UPI) | 1 |
| 04_knowledge_base/Mesh architecture | 1 |
| 04_knowledge_base/AMD EPYC Genoa | 1 |
| 04_knowledge_base/Process node | 1 |
| 04_knowledge_base/Memory Channel | 1 |
| 04_knowledge_base/Granite Rapids | 1 |
| 04_knowledge_base/矽晶圓 | 1 |
| 04_knowledge_base/Photomask Set | 1 |
| 04_knowledge_base/Scribe line | 1 |
| 04_knowledge_base/GPU | 1 |
| 04_knowledge_base/Xeon | 1 |
| 04_knowledge_base/Reticle | 1 |
| 04_knowledge_base/Multi-Die Fabric IO | 1 |
| 04_knowledge_base/Sierra Forest | 1 |