2022-08-30_astera-labs-is-first-to-cxl-memory
Canonical Target Counts
| Target | Occurrences |
|---|
| 04_knowledge_base/CXL | 23 |
| 04_knowledge_base/Memory Pooling | 11 |
| 02_companies/Marvell | 6 |
| 04_knowledge_base/DRAM | 6 |
| 02_companies/AMD | 5 |
| 04_knowledge_base/Memory Expander | 5 |
| 04_knowledge_base/ASIC | 4 |
| 04_knowledge_base/CPU | 4 |
| 04_knowledge_base/Sapphire Rapids | 3 |
| 02_companies/INTC | 3 |
| 04_knowledge_base/PCIe | 3 |
| 04_knowledge_base/Astera Labs Leo | 3 |
| 04_knowledge_base/Tanzanite Silicon | 3 |
| 02_companies/MU | 2 |
| 04_knowledge_base/FPGA | 2 |
| 02_companies/Rambus | 2 |
| 04_knowledge_base/AMD EPYC Genoa | 2 |
| 04_knowledge_base/GPU | 2 |
| 02_companies/MCHP | 2 |
| 02_companies/000660 | 2 |
| 04_knowledge_base/AMD EPYC Bergamo | 2 |
| 04_knowledge_base/Memory Accelerator | 2 |
| 04_knowledge_base/Smart Retimer | 2 |
| 02_companies/MSFT | 1 |
| 04_knowledge_base/MI300 | 1 |
| 04_knowledge_base/Design IP | 1 |
| 04_knowledge_base/JEDEC | 1 |
| 04_knowledge_base/DDR5 | 1 |
| 04_knowledge_base/Hyperscaler | 1 |
| 04_knowledge_base/DDR4 | 1 |
| 04_knowledge_base/CPO | 1 |
| 04_knowledge_base/DDR | 1 |
| 04_knowledge_base/Semiconductor Fab | 1 |
| 04_knowledge_base/Merchant Silicon | 1 |
| 04_knowledge_base/Emerald Rapids | 1 |
| 04_knowledge_base/Memory Channel | 1 |